Dedicated interprocessor messaging interconnects frequently are used in multi-processor systems to communicate messages between processors. Typically, the interprocessor messaging interconnect is implemented as a dedicated interconnect separate from other interconnects, such as the coherence mechanism used to facilitate cache coherency in a multi-processor system having shared memory. In certain multiprocessing environments, such as in systems utilizing virtual processors, the routing of inter-processing messages can be complex, which impedes efficient operation. For message-passing between virtual processors, a conventional dedicated interprocessor messaging interconnect often must have a priori knowledge of the physical identifiers (IDs) of the virtual processor, as well as knowledge of the interconnect topology and routing. Acquiring this information and configuring the message routing therefore can require a substantial number of memory accesses, thereby reducing the overall bandwidth of the processor-memory connection. This problem is exacerbated during start-up as the routing tables of the interprocessor messaging connect may not yet be complete or accurate. Further, in some implementations, the dedicated interprocessor messaging interconnect is subject to security breaches due to their reliance on generic messages to communicate between a messaging agent and a security device. Unauthorized access to the security device therefore can be accomplished by transmitting fake messages that take advantage of the generic nature of the message format. Accordingly, an improved technique for interprocessor message passing would be advantageous.
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